1. Field of the Invention
The present invention relates to a liquid crystal display, and more particularly, to a data driver and a liquid crystal display using the same which can improve the image quality. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for adjusting chromaticity in a liquid crystal display.
2. Discussion of the Related Art
In general, a liquid crystal display (LCD) generates images by controlling light transmittance of liquid crystal cells according to video signals. An active matrix liquid crystal display, which includes switching elements formed respectively in liquid crystal cells, is suitable to display moving images. Thin film transistors (TFT) are typically used as the switching elements in the active matrix liquid crystal display.
FIG. 1 shows a schematic diagram of an apparatus for driving an LCD according to the related art. As shown in FIG. 1, the related art apparatus for driving an LCD includes an image display unit 10, a data driver 20, a gate driver 30, and a timing controller 40. The image display unit 10 includes liquid crystal cells formed in areas defined by gate lines GL1 to GLn crossing data lines DL1 to DLm. The data driver 20 supplies analog video signals to the data lines DL1 to DLm. The gate driver 30 supplies scan pulses to the gate lines GL1 to GLn. The timing controller 40 aligns externally provided source data RGB to supply aligned data to the data driver 20, generates data control signals DCS to control the data driver 20, and generates gate control signals GCS to control the gate driver 30.
The image display unit 10 includes a transistor array substrate (not shown) and a color filter array substrate (not shown) that are affixed together. Spacers (not shown) maintain a cell gap between the two array substrates, and a liquid crystal (not shown) is filled into the gap provided by the spacers. Liquid crystal cells are formed respectively in areas defined by the n-th gate lines GL1 to GLn crossing the m-th data lines DL1 to DLm. Thin film transistors (TFTs) are connected the n-th gate lines GL1 to GLn and the m-th data lines DL1 to DLm in each of the liquid crystal cells. In response to scan pulses from the gate lines GL1 to GLn, the TFTs provide data signals from the data lines DL1 to DLm to the liquid crystal cells. Each of the liquid crystal cells includes a pixel electrode connected to a corresponding TFT and a common electrode, which face each other with a liquid crystal therebetween. Thus, each liquid crystal cell can be equivalently expressed as a liquid crystal capacitor Clc. Each liquid crystal cell also includes a storage capacitor Cst that is connected to a previous gate line to maintain a data signal with which the liquid crystal capacitor Clc is charged until the liquid crystal capacitor Clc is charged with a next data signal.
The timing controller 40 arranges source data RGB input from the outside so as to be suitable to drive the image display unit 10 and provides such arranged source data RGB to the data driver 20. Using a main clock MCLK, a data enable signal DE, and horizontal and vertical synchronization signals Hsync and Vsync, the timing controller 40 generates a data control signal DCS and a gate control signal GCS to control the drive timings of the data driver 20 and the gate driver 30.
The gate driver 30 includes a shift register that sequentially generates scan pulses (i.e., high gate pulses) in response to a gate start pulse GSP and a gate shift clock GSC included in the gate control signal GCS from the timing controller 40. The gate driver 30 sequentially provides the high gate pulses to gate lines GL1 to GLn in the image display unit 10 to turn on TFTs connected to the gate lines GL1 to GLn.
The data driver 20 converts the arranged data signals Data from the timing controller 40 to analog video signals corresponding to the data control signal DCS received from the timing controller 40. The data driver 20 provides the analog video signals, corresponding to a single horizontal line, to the data lines DL1 to DLm every horizontal period during which a single scan pulse is provided. In response to a polarity control signal POL, the data driver 20 reverses the polarity of the analog video signals provided to the data line DL1 to DLm on a line by line basis.
FIG. 2 is a block diagram of the data driver shown in FIG. 1. As shown in FIG. 2, the data driver 20 includes a shift register 21, a first latch 22, a second latch 23, a gamma voltage generator 24, and a digital to analog converter (DAC) 26. The shift register 21 generates sampling signals using a source shift clock SSC and a source start pulse SSP included in the data control signal DCS from the timing controller 40. Specifically, the shift register 21 generates sampling signals by shifting the source start pulse SSP in response to the source shift clock SSC and sequentially provides the sampling signals to the first latch 22. The first latch 22 sequentially samples the arranged data signals Data received from the timing controller 40 in response to the sampling signals from the shift register 21 and provides the sampled data signals to the second latch 23. The second latch 23 stores the sampled data signals received from the first latch 22 on a line by line basis and simultaneously outputs the stored data signals, corresponding to a single line, to the DAC 26 in synchronization with a source output enable signal SOE included in the data control signal DCS.
FIGS. 3A and 3B illustrate the gamma voltage generator shown in FIG. 2. The gamma voltage generator 24 generates a plurality of positive gamma voltages Pgma and a plurality of negative (−) gamma voltages Ngma at voltage divider nodes between a plurality of resistors connected in series between first and second voltages VH and VL and provides the positive and negative gamma voltages Pgma and Ngma to the DAC 26. To generate these voltages, the gamma voltage generator 24 includes a positive gamma voltage generator 24P as shown in FIG. 3A, which generates a plurality of positive gamma voltages Pgma, and a negative gamma voltage generator 24N as shown in FIG. 3B, which generates a plurality of negative (−) gamma voltages Ngma.
As shown in FIG. 3A, the positive gamma voltage generator 24P includes a positive resistor set 50P, a positive decoder 52P, and a positive gray amplifier 54P. The positive resistor set 50P includes a plurality of resistors connected in series between the first and second voltages VH and VL and outputs n positive divided voltages PV1 to PVn using the resistors connected in series. The positive decoder 52P decodes the n divided voltages PV1 to PVn received from the positive resistor set 50P and outputs m positive reference gamma voltages PVref1 to PVrefm. The positive gray amplifier 54P generates a plurality of positive gamma voltage Pgma using the m positive reference gamma voltages PVref1 to PVrefm output from the positive decoder 52P.
The positive resistor set 50P includes a plurality of resistors connected in series between a first voltage VH and a second voltage VL lower than the first voltage VH. The positive resistor set 50P provides a plurality of different positive divided voltages PV1 to PVn, generated at the voltage divider nodes between the resistors through voltage division corresponding to resistances of the resistors, to the positive decoder 52P. The positive resistor set 50P adjusts the resistances of the resistors in response to a curve adjustment signal GAS and an amplitude adjustment signal AAS received from the outside, thereby adjusting a gamma curve and a gamma voltage amplitude.
The positive decoder 52P decodes a plurality of positive divided voltages PV1 to PVn received from the positive resistor set 50P in response to a fine adjustment signal FAS received from the outside and generates m positive reference gamma voltages PVref1 to PVrefm. To accomplish this, the positive decoder 52P includes a plurality of decoders that generates m-2 positive reference gamma voltages PVref2 to PVrefm-1 except the highest and lowest positive reference gamma voltages PVref1 and PVrefm.
The positive gray amplifier 54P further divides m positive reference gamma voltages PVref1 to PVrefm received from the positive decoder 52P and generates a plurality of positive gamma voltages Pgma corresponding to gray levels of the data signals Data to be provided to the data driver 20. The positive gray amplifier 54P provides the positive gamma voltages Pgma to the DAC 26, as shown in FIG. 2.
As shown in FIG. 3B, the negative gamma voltage generator 24N includes a negative resistor set 50N, a negative decoder 52N, and a negative gray amplifier 54N. The negative resistor set 50N includes a plurality of resistors connected in series between the first and second voltages VH and VL and outputs n negative divided voltages NV1 to NVn using the resistors connected in series. The negative decoder 52N decodes the n divided voltages NV1 to NVn received from the negative resistor set 50N and outputs m negative reference gamma voltages NVref1 to NVrefm. The negative gray amplifier 54N generates a plurality of negative gamma voltage Ngma using the m negative reference gamma voltages NVref1 to NVrefm output from the negative decoder 52N.
The negative resistor set 50N includes a plurality of resistors connected in series between a first voltage VH and a second voltage VL lower than the first voltage VH. The negative resistor set 50N provides a plurality of different negative divided voltages NV1 to NVn, generated at the voltage divider nodes between the resistors through voltage division corresponding to resistances of the resistors, to the negative decoder 52N. The negative resistor set 50N adjusts the resistances of the resistors in response to a curve adjustment signal GAS and an amplitude adjustment signal AAS received from the outside, thereby adjusting the gamma curve and the gamma voltage amplitude.
The negative decoder 52N decodes a plurality of negative divided voltages NV1 to NVn received from the negative resistor set 50N in response to a fine adjustment signal FAS received from the outside and generates m negative reference gamma voltages NVref1 to NVrefm. To accomplish this, the negative decoder 52N includes a plurality of decoders that generates m-2 negative reference gamma voltages NVref2 to NVrefm-1 except the highest and lowest negative reference gamma voltages NVref1 and NVrefm.
The negative gray amplifier 54N further divides m negative reference gamma voltages NVref1 to NVrefm received from the negative decoder 52N and generates a plurality of negative gamma voltages Ngma corresponding to gray levels of the data signals Data to be provided to the data driver 20. The negative gray amplifier 54N provides the negative gamma voltages Ngma to the DAC 26, as shown in FIG. 2.
Using a plurality of positive gamma voltages Pgma and a plurality of negative gamma voltages Ngma received from the gamma voltage generator 24, the DAC 26 converts data signals received from the second latch 23 to positive or negative analog video signals. The DAC 26 simultaneously outputs the analog video signals, corresponding to a single line, to the data lines DL1 to DLm. The DAC 26 generates positive or negative video signals in response to a polarity control signal POL included in the data control signal DCS from the timing controller 40.
As described above, the related art data driver 20 performs digital to analog conversion using positive and negative gamma voltages Pgma and Ngma produced by a single positive resistor set 50P and a single negative resistor set 50N.
In the meantime, red R, green G, and blue B color filters are manufactured corresponding to chromaticity coordinates of red, green, and blue colors for the related art liquid crystal display. However, the related art liquid crystal display uses the same gamma voltage for the red, green, and blue liquid crystal cells despite that these cells have different electro-optical characteristics. Thus, the related art liquid crystal display cannot accomplish individual gamma voltages of red, green, and blue colors and cannot adjust individual chromaticity coordinates of red, green, and blue colors. In addition, R, G, and B color characteristics may vary slightly due to small variations in the common voltage during line-inversion operation of the image display unit 10 in the related art liquid crystal display, thereby reducing the image quality. Further, both the positive and negative gamma voltages Pgma and Ngma are provided to the DAC 26 in the related art liquid crystal display, thereby complicating the structure of the DAC 26 and increasing the size thereof.